Very Large Scale Integration (VLSI) circuits are designed with the use of Electronic Design Automation (EDA) tools, also called Computer Aided Design (CAD) tools. Typically, the design process begins with a circuit being specified in a Hardware Description Language (HDL), such as Verilog or VHDL. The HDL description is a set of statements in a computer language format that define the functional operation to be performed by the circuit.
An HDL circuit simulator is used to run a circuit simulation of the HDL description. Modifications to the HDL description are made based upon the results of the HDL circuit simulation.
In addition to its function as a simulator of an HDL description, the HDL circuit simulator is used to generate a netlist. A netlist defines the components and interconnections between the components required to implement the functional operation specified in the HDL circuit description.
Once a netlist has been generated, there are a number of commercially available "silicon compilers", also called "place and route tools", that are used to convert the netlist into a semiconductor circuit layout. The semiconductor circuit layout specifies the physical implementation of the circuit in silicon, or some other semiconductive material. The semiconductor layout includes metal conductive paths to deliver power to different cells in the circuit. In addition, the semiconductor layout includes a set of power trunks that are used to delivery power to the metal conductive paths.
The metal conductive paths and power trunks of a circuit constitute a power network. While there are a number of known EDA tools to test the logical operation of a VLSI circuit, EDA tools to test the operation of a power network of a VLSI circuit are not prevalent. Using existing EDA tools to test the operation of a power network is computationally expensive. The computational expense associated with prior art devices is attributable to the fact that there is a large amount of conductive metal in the power network that must be analyzed. Thus, it would be highly desirable to provide a method and apparatus that reduces the complexity of analyzing the power network of a VLSI circuit.
Two major concerns in analyzing the efficiency of a power network are voltage drop and electromigration. Excessive voltage drop in a circuit must be avoided so that the circuit elements at the physical center of a chip receive sufficient voltage. In other words, if the voltage drop caused by the path resistance to the center of the chip is too large, then the voltage received by the circuit elements at the center of the chip will not be sufficient. Consequently, it would be desirable to provide a method and apparatus to efficiently analyze the voltage drops of a power network in order to identify excessive voltage drops at the nodes of the power network.
The second salient concern in analyzing the efficiency of a power network is to assess whether electromigration will occur in the power network. If the current density driven through a piece of conductive metal is too high, then the atoms in the metal migrate along the conductive metal. This phenomenon, known as electromigration, eventually results in the deterioration of the conductive metal and the failure of the semiconductor circuit. Consequently, an assessment of a power network must include the identification of all regions of the power network that are susceptible to electromigration.